library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity RCA is
generic(N : integer := 8);
port(	A_rca : in  std_logic_vector (N-1 downto 0);
		B_rca : in  std_logic_vector (N-1 downto 0);
		S_rca : out std_logic_vector (N-1 downto 0);
		C_i   : in  std_logic;
		C_o   : out std_logic
);
constant N_num : integer := N/4;
end RCA;

architecture Structural of RCA is
component CLA
port( A_in  : in  std_logic_vector (3 downto 0);
      B_in  : in  std_logic_vector (3 downto 0);
      S_out : out std_logic_vector (3 downto 0);
		C_int : in  std_logic;
      C_out : out std_logic
);
end component;

signal carries : std_logic_vector(N_num downto 0) := (others => '0');
begin

carries(0) <= C_i;

ADD_GEN: for i in 1 to N_num generate
	CLA_num: CLA port map(A_rca((i*4)-1 downto (i-1)*4), B_rca((i*4)-1 downto (i-1)*4), S_rca((i*4)-1 downto (i-1)*4),carries(i-1), carries(i));
end generate;

C_o <= carries(N_num);

end Structural;
